#include "precomp.h"
#include <sstream>

struct CacheLine
{
	uint tag; // adress
	union dataline{
		char c[60];
		uint u[15];
		int i[15];
	} data;
	//uint data; // info dit moet niet 1 uint zijn maar alle rest van de LineSize die overblijft nadat de tag er vanafgetrokken is. na de tag van 2^4 bits zijn er nog 60 bytes over?
#pragma region JPCacheline
	//string tag; //uint?
	//int data; //uint?
#pragma endregion
};

//Intel i7 
#pragma region M&MCaches
const int LineSize = 64; // 64 bytes adress + data
const int Offset = (int)log2((double)LineSize); // bits needed for offset number
//L1
const int L1CacheSize = 32; // 32 KB
const int L1Associativity = 8; // 8 sets
const int L1CacheRows = L1CacheSize * 1024 / ((LineSize) * L1Associativity); // aantal rows
const int L1Index = (int)ceil(log2((double)L1CacheRows)); // bits needed for line number

CacheLine L1[L1CacheRows][L1Associativity];
//L2

//L3

#pragma endregion

#pragma region JPCaches
////Caches
////L1 Cache
//const int l1CacheWay = 4;
//const int l1CacheSize = 64;
//const int l1LineSize = 4;
//const int l1Sets = l1CacheSize / (l1LineSize * l1CacheWay);
//const int l1Index = (int)ceil(log2((double)l1Sets)/(log2((double)16)));
//const int l1Offset = (int)log2((double)l1LineSize);
////L2 Cache 
//const int l2CacheWay = 8;
//const int l2CacheSize = 256;
//const int l2LineSize = 4;
//const int l2Sets = l2CacheSize / (l2LineSize * l2CacheWay);
//const int l2Index = (int)ceil(log2((double)l2Sets) / (log2((double)16)));
//const int l2Offset = (int)log2((double)l2LineSize);
////L3 Cache
//const int l3CacheWay = 16;
//const int l3CacheSize = 2048;
//const int l3LineSize = 4;
//const int l3Sets = l3CacheSize / (l3LineSize * l3CacheWay);
//const int l3Index = (int)ceil(log2((double)l3Sets) / (log2((double)16)));
//const int l3Offset = (int)log2((double)l3LineSize);
//
//
//CacheLine l1Cache[l1Sets][l1CacheWay]; //kloppen deze grotes? is het niet [64] bij [4]?
//CacheLine l2Cache[l2Sets][l2CacheWay]; //kloppen deze grotes? is het niet [256] bij [8]?
//CacheLine l3Cache[l3Sets][l3CacheWay]; //kloppen deze grotes? is het niet [2048] bij [16]?
#pragma endregion


int READ(int* address) //uint?
{
#pragma region M&MReadNotesL1find
	uint linenummer = (((int)address >> Offset) & 0x3F); // get linenummer so bitshift 6 and bitmask 6 to get the 6 bits that represent the line nr
	
	for (int i = 0; i < L1Associativity; i++) // go through the different sets
	{
		if ((L1[linenummer][i].tag >> 31)) // look if there is already input (is the input valid?)
		{
			if (((L1[linenummer][i].tag << 2 >> (Offset + 2))) == ((int)address << 2 >> (Offset + 2))) //? dirtybit << 2 >> Offset+2 // look if the tag is there
			{
				//yeeh find ^^, cookie
				int intreturn = (L1[linenummer][i].data.i[(int)address & 0x3F]);// >> Offset); TODO offset
				return intreturn;
			}
		}
	}

#pragma endregion

#pragma region MarelReadNotesrty1
	// all notes take a 32 bit adress into acount that in strucktered like this:
	// 31 = valid|30 = dirty|29 ... 13 = tag|12 ... 6 = line nr|5 ... 0 = offset
	// offset (welke groep)
	// find the offset by using a bitmask in this case the bitmask will be 0x20 this gets bit 0 till 6 (in need of chance when using more or less cachelines.
	//for (uint i = 0; i << l1CacheWay; i++) // go though the different sets 
	//{
	//
	//}
	// line nr (welke set in de groep)

	// tag (rest van het adres + valid en dirty)

	// 1001010 >> 6
	//  	0000001 == 1
#pragma endregion

#pragma region JPReadCode
	////No idea how else to work on the address
	////Converted it to string and worked on it like that
	//string addr;
	//std::stringstream stream;
	//stream << address;
	//stream >> addr;
	//stream.str(std::string());
	//stream.clear();

	////Getting the various parts of address for L1
	//string l1SetAddress = addr.substr(addr.length() - l1Index - l1Offset, l1Index);
	//int l1SetIndex;
	//stream << std::hex << l1SetAddress;
	//stream >> l1SetIndex;
	//stream.str(std::string());
	//stream.clear();
	//string l1Tag = addr.substr(0, addr.length() - l1Index - l1Offset);

	//for (int i = 0; i < l1CacheWay; i++)
	//	if (l1Cache[l1SetIndex][i].tag == l1Tag)
	//		return l1Cache[l1SetIndex][i].data; //L1 Cache Hit
	////L1 Cache Miss

	////Getting the various parts of address for L2
	//string l2SetAddress = addr.substr(addr.length() - l2Index - l2Offset, l2Index);
	//int l2SetIndex;
	//stream << std::hex << l2SetAddress;
	//stream >> l2SetIndex;
	//stream.str(std::string());
	//stream.clear();
	//string l2Tag = addr.substr(0, addr.length() - l2Index - l2Offset);

	//for (int i = 0; i < l2CacheWay; i++)
	//	if (l2Cache[l2SetIndex][i].tag == l2Tag)
	//		return l2Cache[l2SetIndex][i].data; //L2 Cache Hit
	////L2 Cache Miss

	////Getting the various parts of address for L3
	//string l3SetAddress = addr.substr(addr.length() - l3Index - l3Offset, l3Index);
	//int l3SetIndex;
	//stream << std::hex << l3SetAddress;
	//stream >> l3SetIndex;
	//stream.str(std::string());
	//stream.clear();
	//string l3Tag = addr.substr(0, addr.length() - l3Index - l3Offset);

	//for (int i = 0; i < l3CacheWay; i++)
	//	if (l3Cache[l3SetIndex][i].tag == l3Tag)
	//		return l3Cache[l3SetIndex][i].data; //L3 Cache Hit
	////L3 Cache Miss
#pragma endregion

	// prevent ReadFromRAM using caching
	return ReadFromRAM( address );	
}

void WRITE( int* address, int value ) //(uint, int? value)?
{
#pragma region M&MWriteNotesL1mod
	uint linenummer = (((int)address >> Offset) & 0x3F); // get linenummer so bitshift 6 and bitmask 6 to get the 6 bits that represent the line nr

	for (int i = 0; i < L1Associativity; i++) // go through the different sets
	{
		if ((L1[linenummer][i].tag >> 31)) // look if there is already input (is the input valid?)
		{
			if ((L1[linenummer][i].tag << 2 >> (Offset + 2)) == ((int)address << 2 >> (Offset + 2))) //? dirtybit << 2 >> Offset+2 // look if the tag is there
			{
				//yeeh find ^^, cookie
				L1[linenummer][i].data.i[(int)address & 0x3F] = value;
				//L1[linenummer][i].tag |= 0x3FFE7960; // setting the dirty bit to true
				L1[linenummer][i].tag |= 1 << 31; // setting the dirty bit to true
				return;
			}
		}
	}
#pragma endregion

#pragma region M&MWriteNotesL1empty
		for (int i = 0; i < L1Associativity; i++) // go through the different sets
		{
			if (!(L1[linenummer][i].tag >> 31)) // look if there is already input (is the input valid?)
			{
				L1[linenummer][i].tag = (int)address;
				L1[linenummer][i].data.i[(int)address & 0x3F] = value;
				L1[linenummer][i].tag |= 3 << 30;
				return;
			}
		}
#pragma endregion

#pragma region M&MWriteNotesL1Eviction
	int slot = EvictionPolicy(); // bepaal via de eviction policy het correcte slot
	if (L1[linenummer][slot].tag << 1 >> 31); // al er in dat slot een dirty zit moet deze eerst naar "RAM worden geschreven"
	{
		int* addresscounter = address;
		for (int i = 0; i < 15; i++)
		{
			WriteToRAM(addresscounter, L1[linenummer][slot].data.i[i]);
			addresscounter++;
		}
	}
	L1[linenummer][slot].tag = (int)address; // vul het stukje cache in.
	L1[linenummer][slot].data.i[(int)address & 0x3F] = value; // TODO
	L1[linenummer][slot].tag |= 3 << 29;
#pragma endregion


	// prevent WriteToRAM using caching
    //WriteToRAM( address, value );
}

int EvictionPolicy()
{
#pragma region random
	return rand() % 8; // kies een random getal tussen de 0 en 7
#pragma endregion
}